The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A time-interleaved analog-to-digital converter (ADC) includes multiple sub-ADCs that operate in parallel. Interleaving errors may be caused by mismatch in the parallel sub-ADCs. More particularly, the parallel sub-ADCs of the time-interleaved ADC have offset, gain, and timing mismatches. For high speed ADCs operating with radio-frequency (RF) input signals, the timing mismatch may be a particularly challenging problem.